54SXxx
Actel
92.55kb
General purpose sdram controller. This is the system clock. The controller can transfer data at this rate during bursts. This is a reset signal. Assertion of this sig
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📁 Related Datasheet
54SXxx - FPGAs
(Actel)
v3.1
54SX Family FPGAs
Le a di ng E dg e P er f or m a nc e F ea t u r es
• 320 MHz Internal Performance • 3.7 ns Clock-to-Out (Pin-to-Pin) • 0.1 ns.
54SXxxA - SX-A Family FPGAs
(Actel)
v5.1
SX-A Family FPGAs
Leading-Edge Performance
• • 250 MHz System Performance 350 MHz Internal Performance • • • • • • • • • •
™
Specifications
• .
54S04 - HEX INVERTING GATES
(National Semiconductor)
DM54S04 DM74S04 Hex Inverting Gates
DM54S04 DM74S04 Hex Inverting Gates
General Description
This device contains six independent gates each of which .
54S08 - Quad 2-Input AND Gates
(National Semiconductor)
DM54S08 DM74S08 Quad 2-Input AND Gates
DM54S08 DM74S08 Quad 2-Input AND Gates
General Description
This device contains four independent gates each o.
54S08 - Quadruple 2-Input Positive-AND Gates
(Texas Instruments)
SN5408, SN54LS08, SN54S08
SN7408, SN74LS08, SN74S08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SDLS033 – DECEMBER 1983 – REVISED MARCH 1988
PRODUCTION DATA.
54S10 - STTL type three 3-input NAND gate
(TW)
54S10/74S10 STTL 3 ： tpd=3ns Pd=19mW/ （1/3）
： ： ：
B H × L × Y L H H H
A H L × ×
C H × × L
74Ⅱ Vcc VIH VIL IOH IOL TA -40 4.75 2 0..
54S112 - STTL double-J-K flip-flop
(TW)
54S112/74S112 STTL J－K （、 ） ： f =125MHz Pd=75mW
PRE
K × × × L L H H ×
CLR
CLK
× × × ↓ ↓ ↓ ↓ H
J × × × L H L H ×
H= L=
Q
H L H* Q.
RH035047 - STTL type 3-to-8 line decoder/demodulator
(BDTIC)
54S138/74S138 STTL 3 -8 / ：
· ·,/ ·
： tpd=8ns() tpd=7ns() Pd=245mW
：
S138 , ,。 , , 。 S138 , 8 。 , 24 ; 32 ,。,。
.BDTIC.
BDTIC
.
54S15 - STTL type three 3-input AND gate
(TW)
54S15/74S15 STTL 3 (OC) ： tpd=5.5ns Pd=29mW/ （1/3）
：
： ：
A H L × × B H × L × C H × × L Y H L L L
：
74Ⅱ Vcc VIH VIL VOH IOL TA -40 4.7.
54S161 - Synchronous 4-Bit Binary Counters
(National Semiconductor)
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