54SXxx, 54SX08 Datasheet - Actel

54SXxx General Purpose SDRAM Controller

This is the system clock. The controller can transfer data at this rate during bursts. This is a reset signal. Assertion of this signal causes the SDRAM to be initialized. A pulse on this signal causes the Controller to prepare the SDRAM for a cycle. This signal defines the type of cycle started wh.

v2.0 General-Purpose SDRAM Controller SD R A M Co n t r o l l er Fu nc t i o na l D es cr i p t i o n The general-purpose SDRAM controller is designed to provide simplified control of many different sizes of SDRAMs. The controller architecture provides control for data bursts by linearly incrementing the address. The user starts a burst at a specified address and the burst continues until the user terminates it. SD R A M Co n t r o l l er Si g na l s CLK RESET_N ACTIVATE WR_CYC ADDR CYC_DONE .

54SX08_Actel.pdf