UT8SF2M40 - 80Megabit Flow-thru SSRAM

Aeroflex Circuit Technology

Datasheet Details

Part number	UT8SF2M40
Manufacturer	Aeroflex Circuit Technology
File Size	398.33 KB
Description	80Megabit Flow-thru SSRAM
Datasheet	UT8SF2M40-AeroflexCircuitTechnology.pdf

Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK.

 Synchronous SRAM organized as 2Meg words x 40bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 80MHz bus operations  Internally self-timed output buffer control eliminates the need for synchronous output enable  Registered inputs and outputs for flow-thru operation  Single 2.5V to 3.3V supply  Clock-to-output time - Clk to Q = 12ns  Clock Enable (CEN) pin to enable clock and suspend operation  Synchronous self-t.

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Published: Oct 4, 2016 |