UT8SP2M48 Datasheet (Aeroflex Circuit Technology)

UT8SP2M48, 96Megabit Pipelined SSRAM

Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK.

Used in conjunction with CS1 and CS2 to select or deselect the device.

Chip Enable 1 Input, Active HIGH: Sampled on the rising edge of CLK.

Used in conjunction with CS0 and CS2 to select or deselect the device.

Chip Enable 2 Input,

UT8SP2M48 Features

*  Synchronous SRAM organized as 2Meg words x 48bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 133MHz bus operations  Internally self-timed output buffer control eliminates the need for synchronous output enable  Regist