UT8SP2M48 - 96Megabit Pipelined SSRAM

Aeroflex Circuit Technology

Datasheet Details

Part number	UT8SP2M48
Manufacturer	Aeroflex Circuit Technology
File Size	323.13 KB
Description	96Megabit Pipelined SSRAM
Datasheet	UT8SP2M48-AeroflexCircuitTechnology.pdf

Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK.

 Synchronous SRAM organized as 2Meg words x 48bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 133MHz bus operations  Internally self-timed output buffer control eliminates the need for synchronous output enable  Registered inputs and outputs for pipelined operation  Single 2.5V to 3.3V supply  Clock-to-output time - Clk to Q = 7ns  Clock Enable (CEN) pin to enable clock and suspend operation  Synchronous self-t.

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Published: Oct 4, 2016 |