Description
6 Functional Description 10 Media Independent Interface (MII) 10 100Base-X Module 11 100Base-X Receiver 14 100Base-X Link Monitor 15 100Base-TX Transceiver 16 10Base-T Module 16 Clock Synthesizer 18 Autonegotiation 18 Reset Operation 19 100Base-X PCS Configuration 20 MII Registers 21 dc and ac Specifications 31 Absolute Maximum Ratings 31 Clock Timing 32 Outline Diagram 43 64-Pin TQFP 43 Ordering Information 44
Tables
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Table 1. Twisted-Pair Magnetic Interface 5 Table 2. Twisted
Features
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Single-chip integrated physical layer and transceiver for 10Base-T and/or 100Base-T functions
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IEEE 802.3 compatible 10Base-T and 100Base-T physical layer interface and ANSI X3.263 TP-PMD compatible transceiver
Built-in analog 10 Mbits/s receive filter, eliminating the need for external filters Built-in 10 Mbits/s transmit filter 10 Mbits/s PLL exceeding tolerances for both preamble and data jitter
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