AS4C8M16S Datasheet (Alliance Semiconductor) - 128M

AS4C8M16S, 128M - 8M x 16 bit Synchronous DRAM

Table 3.

Pin Details Symbol CLK Type Input Description Clock: CLK is driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CLK.

CLK also increments the internal burst counter and controls the output registers.

Clock Enable: CKE activates (HIGH) and deactivates (LOW

AS4C8M16S Features

* Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 2M word x 16-bit x 4-bank Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop fu