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AS7C1026C Datasheet - Alliance Semiconductor

AS7C1026C 5V 64K x 16 CMOS SRAM

A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabl.

AS7C1026C Features

* JEDEC standard packaging

* ESD protection > _ 2000 volts - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 Pin arrangement 44-Pin SOJ (400 mil), TSOP 2 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2

AS7C1026C Datasheet (287.41 KB)

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Datasheet Details

Part number:

AS7C1026C

Manufacturer:

Alliance Semiconductor

File Size:

287.41 KB

Description:

5v 64k x 16 cmos sram.

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TAGS

AS7C1026C 64K CMOS SRAM Alliance Semiconductor

AS7C1026C Distributor