EP1S40 Datasheet - Altera

EP1S40 (EP1S10 - EP1S80) Stratix Device

on page 2 *71. Deleted the word preliminary from the “specification for the maximum time to relock is 100 µs” on page 2 *88. Added information about differential SSTL and HSTL outputs in “External Clock Outputs” on page 2 *90. Updated notes in Figure 2 *55 on page 2

EP1S40 Features

* on page 1

* 2. Global change from SignalTap to SignalTap II. The DSP blocks in “Features” on page 1

* 2 provide dedicated implementation of multipliers that are now “faster than 300 MHz.” Updated -5 speed grade device information in Table 1-6. Add -8 speed grade device information. Form

EP1S40 Datasheet (3.36 MB)