AD75019 Datasheet | Analog Devices

FEATURES 256 Switches in a 16 ؋ 16 Array Wide Signal Range: to Supply Rails of 24 V or ؎12 V Low On-Resistance: 200 ⍀ Typ TTL/CMOS/Microprocessor-patible Control Lines Serial Input Simplifies Interface Serial Output Allows Cascading for More Channels Low Power Consumption: 2 m W Quiescent pact 44-Lead PLCC X0 Y0 16 ؋ 16 Crosspoint Switch Array AD75019 FUNCTIONAL BLOCK DIAGRAM ANALOG INPUTS/OUTPUTS X15 VDD VSS VCC DGND SERIAL DATA IN SHIFT REGISTER CELL #256 +12V - 12V +5V DGND LATCH ANALOG SWITCH ANALOG OUTPUTS/ INPUTS BUSED CLOCK LINES SERIAL DATA TO NEXT STAGES 16 ؋ 16 ARRAY OF SWITCHES, LATCHES, AND SHIFT REGISTER CELLS (ONLY TWO LOCATIONS ARE SHOWN FOR CLARITY) Y15 ANALOG SWITCH SERIAL DATA FROM PRIOR STAGES BUSED CLOCK LINES SHIFT REGISTER CELL #1 LATCH PARALLEL CLOCK SERIAL CLOCK PCLK SCLK SOUT PRODUCT DESCRIPTION The AD75019 contains 256 analog switches in a 16 × 16 array. Any of the X or Y pins may serve as an input or output. Any or all of the X terminals may be programmed to connect to any or all of the Y terminals. The switches can acmodate signals with amplitudes up to the supply rails and have a typical onresistance of 150 Ω. Data is loaded serially via the SIN input and clocked into an onboard 256-bit shift register via SCLK. When all the switch settings have been programmed, data is transferred into a set of 256 latches via PCLK. The serial shift register is dynamic, so there is a minimum clock rate of 20 k Hz. The maximum clock rate of 5 MHz allows loading times as short as 52 µs. The switch control latches are static and will hold their data as long as power is applied. To extend the number of switches in the array, you may cascade multiple AD75019s. The SOUT output is the end of the shift register, and may be connected to the SIN input of the next AD75019. The AD75019 is fabricated in Analog Devices’ Bi MOS II process. This epitaxial Bi CMOS process features CMOS devices for low distortion switches and bipolar devices for ESD...