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AD7625 - 6MSPS PulSAR Differential ADC

Description

The AD7625 is a 16-bit, 6MSPS, charge redistribution successive approximation register (SAR) architecture, analog-to-digital converter (ADC).

92dB SNR - and in linearity

1LSB.

Features

  • Throughput: 6 MSPS SAR architecture 16-bit resolution with no missing codes SNR: 92 dB Typ, 90dB Min @ 1MHz INL: ±1 LSB Typ, ±2 LSB Max DNL: ±0.3 LSB Typ, ±1 LSB Max Differential input range: ± 4.096V No latency/no pipeline delay (SAR architecture) Serial LVDS interface: Self-clocked mode Echoed-clock mode Reference: Internal 4.096 V External (1.2V) buffered to 4.096 V External 4.096 V Power dissipation 150 mW 32-Lead LFCSP package (5 mm x 5 mm) 16-Bit, 6MSPS PulSAR Differential ADC AD7625 FUNC.

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Other Datasheets by Analog Devices

Part Number Description
AD7621 3 MSPS PulSAR ADC
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com Preliminary Technical Data FEATURES Throughput: 6 MSPS SAR architecture 16-bit resolution with no missing codes SNR: 92 dB Typ, 90dB Min @ 1MHz INL: ±1 LSB Typ, ±2 LSB Max DNL: ±0.3 LSB Typ, ±1 LSB Max Differential input range: ± 4.096V No latency/no pipeline delay (SAR architecture) Serial LVDS interface: Self-clocked mode Echoed-clock mode Reference: Internal 4.096 V External (1.2V) buffered to 4.096 V External 4.096 V Power dissipation 150 mW 32-Lead LFCSP package (5 mm x 5 mm) 16-Bit, 6MSPS PulSAR Differential ADC AD7625 FUNCTIONAL BLOCK DIAGRAM REFIN REF VCM 1.2V BANDGAP IN+ INCAP DAC 2 CLOCK LOGIC VIO CNV D AD7626 SAR SERIAL LVDS DCO CLK Figure 1.
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