HMC6832 Datasheet, Buffer, Analog Devices

HMC6832 Features

• Buffer Ultralow noise floor:
• 165.9 dBc/Hz or
• 165.2 dBc/Hz (LVPECL or LVDS) at 2000 MHz Configurable to LVPECL or pseudo LVDS outputs 2.5 V or 3.3 V LVPECL operation (LVDS 2.5

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HMC6832

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📄 Datasheet

Description:

2:8 differential fanout buffer. The HMC6832 is an input selectable, 2:8 differential fanout buffer designed for low noise clock distribution. The IN_SEL control pin

HMC6832 Application

• Applications SONET, Fibre Channel, GigE clock distribution ADC/DAC clock distribution Low skew and jitter clocks Wireless/wired communications Level

TAGS

HMC6832

Analog Devices

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