* Ultra Low Noise Floor: -166 dBc/Hz @ 2 GHz Wideband: DC - 8 GHz Operating Frequency Flexible Input Interface: LVPECL, LVDS, CML, CMOS Compatible AC or DC Coupling On-Chip Termination 50 or 150 Ω (100/300 Ω Diff.) Multiple Output Drivers: Up to 8 Differential or 16 Single-Ended LVPECL Outputs: 800 mV
HMC987LP5E Datasheet (1.64 MB)
HMC987LP5E
1.64 MB
Low noise 1:9 fanout buffer.
Clock Distribution - SMT
v03.1112
Typical Applications
The is suitable for:
* SONET, Fibre Channel, GigE Clock Distribution
* ADC/DAC.
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