* Monolithic Design for Reliability and Low Cost High Slew Rate: 0.5 V/ s Low Droop Rate TA = 25؇ C: 0.1 mV/ms T A = 125؇ C: 10 mV/ms Low Zero-Scale Error: 4 mV Digitally Selected Hold and Reset Modes Reset to Positive or Negative Voltage Levels Logic Signals TTL and CMOS Compatible Uncommitted Compa
PKD01
429.08 KB
Monolithic peak detector with reset-and-hold mode.
. a U 4 .D at h S a t e e
m o c
Monolithic Peak Detector with Reset-and-Hold Mode PKD01
FUNCTIONAL BLOCK DIAGRAM
+IN
*IN OUTPUT V+ V
.
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