AZP92 Clock Generation Chip

Description

www.DataSheet4U.com ARIZONA MICROTEK, INC.AZP92 ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable .
The AZP92 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function.

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Datasheet Specifications

Part number: AZP92
Manufacturer: Arizona Microtek
File Size: 132.98 KB
Datasheet: AZP92_ArizonaMicrotek.pdf
Description: Clock Generation Chip

Features

* Green and RoHS Compliant / Lead (Pb) Free Package Available 3.0V to 5.5V Operation Selectable Divide Ratio Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Selectable Input Biasing High Bandwidth for ≥1GHz Ava

Applications

* D or D ¯ may be connected directly to VBB to form a single 1880Ω bias resistor. The VBB pin supports 1.5mA sink/source current. Whenever used, the VBB should be bypassed to ground or VCC with a 0.01 μF capacitor. MLP 8, 2x2 mm Package (AZP92NA) The AZP92NA provides a VBB with an 1880Ω internal bias

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