AZP92 Datasheet (Arizona Microtek) - Clock Generation Chip

AZP92, Clock Generation Chip

The AZP92 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function.

The divide ratio is selected with the DIV-SEL pin/pad.

When DIV-SEL is open (NC), the AZP92 functions as a standard receiver.

If DIV-SEL is connected to VEE, it functions as a ÷2 divider.

A selectable enabl

AZP92 Features

* Green and RoHS Compliant / Lead (Pb) Free Package Available 3.0V to 5.5V Operation Selectable Divide Ratio Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Selectable Input Biasing High Bandwidth for ≥1GHz Ava