Download the ATtiny12 datasheet PDF.
This datasheet also covers the ATtiny11 variant, as both devices belong to the same 8-bit microcontroller family and are provided as variant models within a single manufacturer datasheet.
Key Features
Utilizes the AVR® RISC Architecture.
High-performance and Low-power 8-bit RISC Architecture.
90 Powerful Instructions.
Most Single Clock Cycle Execution.
32 x 8 General Purpose Working Registers.
Up to 8 MIPS Throughput at 8 MHz.
Nonvolatile Program and Data Memory.
1K Byte of Flash Program Memory
In-System Programmable (ATtiny12) Endurance: 1,000 Write/Erase Cycles (ATtiny11/12).
Full PDF Text Transcription for ATtiny12 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
ATtiny12. For precise diagrams, and layout, please refer to the original PDF.
Features • Utilizes the AVR® RISC Architecture • High-performance and Low-power 8-bit RISC Architecture – 90 Powerful Instructions – Most Single Clock Cycle Execution – 3...
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ure – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 8 MIPS Throughput at 8 MHz • Nonvolatile Program and Data Memory – 1K Byte of Flash Program Memory In-System Programmable (ATtiny12) Endurance: 1,000 Write/Erase Cycles (ATtiny11/12) – 64 Bytes of In-System Programmable EEPROM Data Memory for ATtiny12 Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security • Peripheral Features – Interrupt and Wake-up on Pin Change – One 8-bit Timer/Counter with Separate Prescaler – On-chip Analog Comparator – Programmable Watchdo
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