Datasheet Details
| Part number | CY3120 |
|---|---|
| Manufacturer | Cypress Semiconductor |
| File Size | 112.69 KB |
| Description | CPLD Development Software for PC |
| Datasheet |
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| Part number | CY3120 |
|---|---|
| Manufacturer | Cypress Semiconductor |
| File Size | 112.69 KB |
| Description | CPLD Development Software for PC |
| Datasheet |
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: Behavioral VHDL and Verilog (IFTHENELSE; CASE) Boolean Aldec Active-HDL™ FSM graphical Finite State Machine editor Structural Verilog and VHDL Designs can include multiple entry methods (but only one HDL language) in a single design. UltraGen™ Synthesis and Fitting Technology: Infers “modules” such as adders, comparators, etc., from behavioral descriptions and replaces them with circuits pre-optimized for the target device.
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