Datasheet Details
| Part number | CY3125 |
|---|---|
| Manufacturer | Cypress Semiconductor |
| File Size | 112.14 KB |
| Description | CPLD Development Tool for Unix |
| Datasheet |
 CY3125 Datasheet
|
|
|
| Part number | CY3125 |
|---|---|
| Manufacturer | Cypress Semiconductor |
| File Size | 112.14 KB |
| Description | CPLD Development Tool for Unix |
| Datasheet |
CY3125 Datasheet
|
|
|
|
: Behavioral VHDL and Verilog (IFTHENELSE; CASE) Boolean Structural Verilog and VHDL DESIGN ENTRY Integers IEEE Standard 1364 Verilog synthesis supports: Reduction and conditional operators Designs can include multiple entry methods (but only one HDL language) in a single design. UltraGen™ Synthesis and Fitting Technology: Infers “modules” such as adders, comparators, etc., from behavioral descriptions a
📁 Similar Datasheet