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CY7C25422KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture

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Description

CY7C25422KV18 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (.

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Datasheet Specifications

Part number
CY7C25422KV18
Manufacturer
Cypress Semiconductor
File Size
557.73 KB
Datasheet
CY7C25422KV18-CypressSemiconductor.pdf
Description
72-Mbit QDR II+ SRAM Two-Word Burst Architecture

Features

* Separate independent read and write data ports
* Supports concurrent transactions
* 333 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz

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