CY7C2563KV18, CY7C2561KV18 Datasheet - Cypress Semiconductor

CY7C2563KV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture

The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II+ architecture. Similar to QDR-II architecture, QDR-II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has.

CY7C2563KV18 Features

* Configurations With Read Cycle Latency of 2.5 cycles: CY7C2561KV18

* 8M x 8 CY7C2576KV18

* 8M x 9 CY7C2563KV18

* 4M x 18 CY7C2565KV18

* 2M x 36 Separate independent read and write data ports

* Supports concurrent transactions 550 MHz clock for high bandwid

CY7C2561KV18_CypressSemiconductor.pdf