CY7C25652KV18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 550 MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
CY7C25632KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C25652KV18, CY7C25632KV18
Cypress Semiconductor
608.41 KB
72-mbit qdr ii+ sram four-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C25652KV18, CY7C25632KV18.
Please refer to the document for exact specifications by model.
CY7C25652KV18 Distributor
📁 Related Datasheet
📌 All Tags
