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CY7C2642KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture

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Description

CY7C2642KV18/CY7C2644KV18 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR® II+ SRAM Two-Word Burst .

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Datasheet Specifications

Part number
CY7C2642KV18
Manufacturer
Cypress Semiconductor
File Size
607.25 KB
Datasheet
CY7C2642KV18-CypressSemiconductor.pdf
Description
144-Mbit QDR II+ SRAM Two-Word Burst Architecture

Features

* Separate independent read and write data ports
* Supports concurrent transactions
* 333-MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz

CY7C2642KV18 Distributors

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Cypress Semiconductor CY7C2642KV18-like datasheet