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CY7C2642KV18 - 144-Mbit QDR II+ SRAM Two-Word Burst Architecture

Cypress Semiconductor

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Datasheet Details

Part number	CY7C2642KV18
Manufacturer	Cypress Semiconductor
File Size	607.25 KB
Description	144-Mbit QDR II+ SRAM Two-Word Burst Architecture
Datasheet	CY7C2642KV18-CypressSemiconductor.pdf

CY7C2642KV18 Product details

Features

Separate independent read and write data ports.
Supports concurrent transactions.
333-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
Available in 2.0-clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed sys.

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Published: Mar 14, 2017 |