* Separate independent read and write data ports
* Supports concurrent transactions
* 333-MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
CY7C2642KV18 Datasheet (607.25 KB)
CY7C2642KV18
Cypress Semiconductor
607.25 KB
144-mbit qdr ii+ sram two-word burst architecture.
CY7C2642KV18/CY7C2644KV18 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR® II+ SRAM Two-Word Burst .
📁 Related Datasheet
CY7C264 8K x 8 Power-Switched and Reprogrammable PROM (Cypress Semiconductor)
CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C261 8K x 8 Power-Switched and Reprogrammable PROM (Cypress Semiconductor)
CY7C263 8K x 8 Power-Switched and Reprogrammable PROM (Cypress Semiconductor)
CY7C265 8K x 8 Registered PROM (Cypress Semiconductor)
CY7C266 8Kx8 Power-Switched and Reprogrammable PROM (Cypress Semiconductor)
CY7C2663KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2163KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
TAGS
Image Gallery
