CY7C2644KV18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 333-MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
CY7C2642KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C2644KV18, CY7C2642KV18
Cypress Semiconductor
607.25 KB
144-mbit qdr ii+ sram two-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C2644KV18, CY7C2642KV18.
Please refer to the document for exact specifications by model.
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CY7C2644KV18 Distributor
