CY7C2644KV18 - 144-Mbit QDR II+ SRAM Two-Word Burst Architecture
CY7C2644KV18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 333-MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
