S71KS512SC0 Datasheet - Cypress Semiconductor

S71KS512SC0, HyperFlash and HyperRAM Multi-Chip Package

SUPPLEMENT S71KS512SC0 S71KL256SC0 S71KL512SC0 HyperFlash™ and HyperRAM™ Multi-Chip Package 1.8V/3V HyperFlash™ and HyperRAM™ Multi-Chip Package 3 .
3 HyperBus MCP Family with HyperFlash and HyperRAM 3 HyperBus MCP 3 V Signal Descriptions 4 HyperBus MCP Block Diagram 5 Physical Interface 6 Hyp.

Features

* operation, and ordering options of the related memories have been enhanced or changed from the standard memory devices incorporated in the MCP. The information contained in this document modifies any information on the same topics established by the documents listed in Table 1 and should be used in

Applications

* operating systems, or tools. Table 1. Affected Documents/Related Documents Title HyperBus™ Specification Low Signal Count, High Performance DDR Bus S26KL512S / S26KS512S / S26KL256S / S26KS256S / S26KL128S / S26KS128S, 512 MBIT (64 MBYTE), 256 Mbit (32 Mbyte), 128 Mbit (16 Mbyte) 1.8V/3.0V HyperFl

S71KS512SC0-CypressSemiconductor.pdf