W162 Datasheet - Cypress Semiconductor

W162 Spread Aware/ Zero Delay Buffer

Reference Input: The output signals QA0:3 through QB0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL. Feedback Output: This signal is used as the feedback internally to establish the propagation delay of nearly 0. Outputs from Bank A: The frequency of the sig.

W162 Features

* Spread Aware™

* designed to work with SSFTG reference signals

* Two banks of four outputs, plus the fed back output

* Outputs may be three-stated

* Available in 16-pin SOIC or SSOP package

* Extra strength output drive available (-19 version)

W162_CypressSemiconductor.pdf