W163 Datasheet - Cypress Semiconductor

W163 Spread Aware/ Zero Delay Buffer

Reference Input: The output signals Q0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL. Outputs: These signals will be synchronous and of equal frequency to the signal input at pin 1. Feedback Output: This output signal does not vary from signals Q0:3 in funct.

W163 Features

* Spread Aware™

* designed to work with SSFTG reference signals

* Outputs may be three-stated

* Available in 8-pin SOIC package

* Extra strength output drive available (-15 version)

* Internal feedback maximized the number of outputs available in 8-pin p

W163_CypressSemiconductor.pdf