Description
Reference Input: The output signals Q0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL.
Features
- Spread Aware™.
- designed to work with SSFTG reference signals.
- Outputs may be three-stated.
- Available in 8-pin SOIC package.
- Extra strength output drive available (-15 version).
- Internal feedback maximized the number of outputs available in 8-pin package
Key Specifications
Operating Voltage: 3.3V±10% Operating Range: 10 < fOUT < 133 MHz Cycle-to-Cycle Jitter: 200 ps Output-to-Output Skew: 250 ps Device-to-Device Skew: 700 ps Propagation De.
W163_CypressSemiconductor.pdf
