W40S11-23 Datasheet - Cypress Semiconductor

W40S11-23 Clock Buffer/Driver

SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within ± 250 ps of each other. Clock Input: This clock input has an input threshold voltage of 1.5V (typ). I2C Data input: Data sho.

W40S11-23 Features

* Thirteen skew-controlled CMOS clock outputs (SDRAM0:12)

* Supports three SDRAM DIMMs

* Ideal for high-performance systems designed around Intel’s latest chip set

* I2C serial configuration interface

* Clock Skew between any two outputs is less than 250 ps

W40S11-23 Datasheet (124.01 KB)