Description
Reference Input: The output signals QA0:3 through QB0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL.
Features
- Spread Aware™.
- designed to work with SSFTG reference signals.
- Two banks of four outputs, plus the fed back output.
- Outputs may be three-stated.
- Available in 16-pin SOIC or SSOP package.
- Extra strength output drive available (-19 version).
- Internal feedback Table 1. Input Logic SEL1 0 0 1 1 SEL0 0 1 0 1 QA0:3 ThreeState Active Active Active QB0:3 ThreeState ThreeState Active Active PLL Shutdown Active, Utilized Shutdown, Bypassed Activ.
W162_CypressSemiconductor.pdf
