* Double-data-rate architecture: two data transfers per clock cycle
* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
PDJ2108DEBG Datasheet (1.91 MB)
PDJ2108DEBG
Deutron Electronics
1.91 MB
2g bits ddr3 sdram.
DATA SHEET
2G bits DDR3 SDRAM
PDJ2108DEBG (256M words × 8 bits) PDJ2116DEBG (128M words × 16 bits)
Specifications
* Density: 2G bits
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