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PDJ2108DEBG - 2G bits DDR3 SDRAM

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PDJ2108DEBG 2G bits DDR3 SDRAM by Deutron Electronics - Datasheet Preview — Datasheet preview – PDJ2108DEBG

Datasheet Details

Part number	PDJ2108DEBG
Manufacturer	Deutron Electronics
File Size	1.91 MB
Description	2G bits DDR3 SDRAM
Datasheet	PDJ2108DEBG Datasheet
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Features

Double-data-rate architecture: two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

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