* Double-data-rate architecture: two data transfers per clock cycle
* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
PDJ2116DEBG Datasheet (1.91 MB)
PDJ2116DEBG
Deutron Electronics
1.91 MB
2g bits ddr3 sdram.
DATA SHEET
2G bits DDR3 SDRAM
PDJ2108DEBG (256M words × 8 bits) PDJ2116DEBG (128M words × 16 bits)
Specifications
* Density: 2G bits
.
📁 Related Datasheet
PDJ2108DEBG 2G bits DDR3 SDRAM (Deutron Electronics)
PD-20 0 Power Dividers / Combiners (Merrimac Industries)
PD-3100 WDM PIN PHOTODIODES (Optoway Technology)
PD-5100 WDM PIN PHOTODIODES (Optoway Technology)
PD-9002GHO Outdoor PoE Passive Hub (Microsemi)
PD-9501GO Power Over Ethernet (Microsemi)
PD-CP42AU Industrial LCD (Canvys)
PD-NPM-0305EP DSL NTU POWER MODULE (PowerDsine)
PD-SSI Digital Process Meter (ASM)
PD001 Single Digit Mini 7 Segment Display (P-tec Corporation)
