M14D2561616A - DDR-II SDRAM

Datasheet Details

JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation. On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition 1KB page size - Row address: A0 to A12 - Column address: A0 to A8 Quad bank operation CAS Latency : 3, 4, 5, 6, 7, 8, 9 Additive Latency: 0, 1, 2,.

📁 M14D2561616A Similar Datasheet

Other Datasheets by ESMT

Published: Sep 20, 2018 |