M14D5121632A-1.8BBG2M, M14D5121632A - DDR-II SDRAM

Datasheet Details

Part number	M14D5121632A-1.8BBG2M, M14D5121632A
Manufacturer	ESMT
File Size	1.00 MB
Description	DDR-II SDRAM
Datasheet	M14D5121632A-ESMT.pdf
Note	This datasheet PDF includes multiple part numbers: M14D5121632A-1.8BBG2M, M14D5121632A. Please refer to the document for exact specifications by model.

JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation. On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 3, 4, 5, 6, 7, 8, 9 Additive Latency: 0, 1, 2, 3, 4, 5, 6, 7 Burst Type : Sequential and Interleave Burst Length.

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Published: Mar 25, 2019 |