M14D5121632A-1.8BG2M Features
* JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation. On-chip DLL Differential clock inputs (CLK and CLK )
Datasheet Details
M14D5121632A-1.8BG2M, M14D5121632A
ESMT
1.00 MB
Ddr-ii sdram.
This datasheet PDF includes multiple part numbers: M14D5121632A-1.8BG2M, M14D5121632A.
Please refer to the document for exact specifications by model.
M14D5121632A-1.8BG2M Distributor
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