55N03L S eptember , 2002 N-Channel Logic Level E nhancement Mode Field E ffect Transistor 4 P R ODUC T S UMMAR Y F E AT UR E S VDS S 30V ID R DS (on) ( m W ) T Y P 12.5 @ VGS = 10V 55A 20 @ VGS = 4.5V S uper high dense cell design for extremely low R DS (ON). High power and current handling capability. TO-220 & TO-263 package. D GS S DB S E R IE S T O -263(DD-P AK ) G D S S DP S E R IE S TO-220 D G S ABS OLUTE MAXIMUM R ATINGS (TC =25 C unless otherwise noted) P arameter Drain-S ource .
