DDU8C3-5050 Datasheet (ETC) - 5-TAP/ 3.3V CMOS-INTERFACED FIXED DELAY LINE

DDU8C3-5050, 5-TAP/ 3.3V CMOS-INTERFACED FIXED DELAY LINE

PIN DESCRIPTIONS The DDU8C3-series device is a 5-tap digitally buffered delay line.

The IN Signal Input signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an T1-T5 Tap Outputs amount determined by the device dash number (See Table).

For dash VDD +3.3 Volts numbers 5020 and

DDU8C3-5050 Features

* Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully CMOS interfaced & buffered 2 10 T L fan-out capability IN T2 T4 GND data 3 ® delay devices, inc. PACKAGES 1 2 3 4 8 7 6 5 VDD T1 T