* -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009 PRODUCT SUMMARY The Q
QL2009-2PB256C Datasheet (272.83 KB)
QL2009-2PB256C
ETC
272.83 KB
3.3v and 5.0v pasic 2 fpga combining speed/ density/ low cost and flexibility.
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS ® QL2009 Ultimate Verilog/VHDL Silicon Solu.
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