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QL2009-XPQ208I

3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility

QL2009-XPQ208I Features

* -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009 PRODUCT SUMMARY The Q

QL2009-XPQ208I General Description

Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-d.

QL2009-XPQ208I Datasheet (272.83 KB)

Preview of QL2009-XPQ208I PDF

Datasheet Details

Part number:

QL2009-XPQ208I

Manufacturer:

ETC

File Size:

272.83 KB

Description:

3.3v and 5.0v pasic 2 fpga combining speed/ density/ low cost and flexibility.
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS ® QL2009 Ultimate Verilog/VHDL Silicon Solu.

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TAGS

QL2009-XPQ208I 3.3V and 5.0V pASIC FPGA Combining Speed Density Low Cost and Flexibility ETC

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