VSC6048 Datasheet - ETC

VSC6048 High-Speed Octal Programmable Timing Generator

Reference Clock Selection Clock multiplication of x8 or x16 may be selected via the FSEL pin, requiring a reference clock of 100 ±2.5MHz or 50 ±1.25MHz, respectively. For system applications with 800MHz on board clock, the CMU can be bypassed by asserting BYP signal and RCK will accept an external 8.

VSC6048 Features

* 8 Fully Integrated Timing Generators for ATE Applications

* 10/5ns Delay Range, 10ps Resolution

* Fully Digital Interface. No Off-Chip DACs or Trim Components Required

* ± 4 LSB Differential Non-Linearity High-Speed Octal Programmable Timing Generator

* 10

VSC6048 Datasheet (204.97 KB)