M13L128168A - DDR SDRAM
ESMT Revision History Revision 1.3 -Revise operation voltage.
(page 5) Revision 1.2 -Changed tWTR from 1 tCK to 2 tCK.
Revision 1.1 -Changed absolute max.
voltage (VIN, VOUT ,VDD ,VDDQ) from 3.6V to 4.0V Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Symbol VIN, VOUT VDD VDDQ Value -0.5 ~ 4.0 -1.0 ~ 4.0 -0.5 ~ 4.0 Unit V V V M13L128168A -Changed operating VDD from 3.135V~3.6V to 3.135V~3.83V -Updated DC current specific
M13L128168A Features
* z z z z z z z z z z z z z z z z z z z z M13L128168A 2M x 16 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe(DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and D
