* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE21AD4AJFA Datasheet (275.82 KB)
EBE21AD4AJFA
Elpida Memory
275.82 KB
2gb registered ddr2 sdram dimm.
DATA SHEET www.DataSheet4U.com 2GB Registered DDR2 SDRAM DIMM EBE21AD4AJFA (256M words × 72 bits, 2 Ranks) Specifications Density: 2GB
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