* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE21AE8ACWA Datasheet (272.36 KB)
EBE21AE8ACWA
Elpida Memory
272.36 KB
2gb registered ddr2 sdram dimm.
DATA SHEET
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2GB Registered DDR2 SDRAM DIMM
EBE21AE8ACWA (256M words × 72 bits, 2 Ranks)
Specifications
* Density: 2GB
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