* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE51AD8AGFA Datasheet (238.53 KB)
EBE51AD8AGFA
Elpida Memory
238.53 KB
512mb registered ddr2 sdram dimm.
PRELIMINARY DATA SHEET www.DataSheet4U.com 512MB Registered DDR2 SDRAM DIMM EBE51AD8AGFA (64M words × 72 bits, 1 Rank) Specifications Dens.
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