* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE51ED8AGWA Datasheet (237.14 KB)
EBE51ED8AGWA
Elpida Memory
237.14 KB
512mb unbuffered ddr2 sdram dimm.
PRELIMINARY DATA SHEET www.DataSheet4U.com 512MB Unbuffered DDR2 SDRAM DIMM EBE51ED8AGWA (64M words × 72 bits, 1 Rank) Specifications Dens.
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