* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE51ED8AJWA Datasheet (267.24 KB)
EBE51ED8AJWA
Elpida Memory
267.24 KB
512mb unbuffered ddr2 sdram dimm.
DATA SHEET www.DataSheet4U.com 512MB Unbuffered DDR2 SDRAM DIMM EBE51ED8AJWA (64M words × 72 bits, 1 Rank) Specifications Density: 512MB <.
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