* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE52UD6AJUA Datasheet (330.66 KB)
EBE52UD6AJUA
Elpida Memory
330.66 KB
512mb ddr2 sdram so-dimm.
DATA SHEET www.DataSheet4U.com 512MB DDR2 SDRAM SO-DIMM EBE52UD6AJUA (64M words × 64 bits, 2 Ranks) Specifications Density: 512MB .
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