EDD5108AGTA - 512M bits DDR SDRAM
DATA SHEET 512M bits DDR SDRAM EDD5108AGTA (64M words × 8 bits) EDD5116AGTA (32M words × 16 bits) Specifications Density: 512M bits Organization ⎯ 16M words × 8 bits × 4 banks (EDD5108AGTA) ⎯ 8M words × 16 bits × 4 banks (EDD5116AGTA) Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) Power supply: VDD, VDDQ = 2.5V ± 0.2V Data rate: 400Mbps/333Mbps/266Mbps (max.) Four internal banks for concurrent operation Interf
EDD5108AGTA Features
* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
* Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
* Data
