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EDD5108AGTA - 512M bits DDR SDRAM

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Elpida Memory

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EDD5108AGTA 512M bits DDR SDRAM by Elpida Memory - Datasheet Preview — Datasheet preview – EDD5108AGTA

Datasheet Details

Part number	EDD5108AGTA
Manufacturer	Elpida Memory
File Size	575.84 KB
Description	512M bits DDR SDRAM
Datasheet	EDD5108AGTA Datasheet
Additional preview pages of the EDD5108AGTA datasheet.

Product details

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture.
Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver.
Data inputs, outputs, and DM are synchronized with DQS.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL.

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Published: Nov 20, 2009 |