* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
* Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
* Data
EDD5108AGTA Datasheet (575.84 KB)
EDD5108AGTA
Elpida Memory
575.84 KB
512m bits ddr sdram.
DATA SHEET 512M bits DDR SDRAM EDD5108AGTA (64M words × 8 bits) EDD5116AGTA (32M words × 16 bits) Specifications Density: 512M bits
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