* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
* Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
* Data
EDD5108AGTA-LI Datasheet (573.52 KB)
EDD5108AGTA-LI
Elpida Memory
573.52 KB
512m bits ddr sdram wtr.
PRELIMINARY DATA SHEET
512M bits DDR SDRAM WTR (Wide Temperature Range)
EDD5108AGTA-LI (64M words × 8 bits) EDD5116AGTA-LI (32M words × 16 bits)
Spec.
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