* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EDJ1108DBSE Datasheet (2.19 MB)
EDJ1108DBSE
Elpida Memory
2.19 MB
128m words x 8 bits 1g bits ddr3 sdram.
DATA SHEET 1G bits DDR3 SDRAM EDJ1108DBSE (128M words × 8 bits) EDJ1116DBSE (64M words × 16 bits) Specifications Density: 1G bits
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