74F109 Datasheet - Fairchild Semiconductor

Dual JK Positive Edge-Triggered Flip-Flop

74F109 General Description

The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs. Asynchron.

74F109 Datasheet (79.72 KB)

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74F109

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Fairchild Semiconductor

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79.72 KB

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Dual jk positive edge-triggered flip-flop.
74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Descripti.

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74F109 Dual Positive Edge-Triggered Flip-Flop Fairchild Semiconductor

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74F109 General Description

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