74F109
Fairchild Semiconductor
79.72kb
Dual jk positive edge-triggered flip-flop. The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent o
📁 Related Datasheet
74F10 - Triple 3-input NAND gate
(NXP)
INTEGRATED CIRCUITS
74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate
Product specification IC15 Data Handbook 1989 Sep 20
Philips Semico.
74F10 - Triple 3-Input NAND Gate
(Fairchild Semiconductor)
74F10 Triple 3-Input NAND Gate
April 1988 Revised July 1999
74F10 Triple 3-Input NAND Gate
General Description
This device contains three independen.
74F10 - Triple 3-Input NAND Gate
(National Semiconductor)
54F 74F10 Triple 3-Input NAND Gate
December 1994
54F 74F10 Triple 3-Input NAND Gate
General Description
This device contains three independent gates.
74F10 - TRIPLE 3-INPUT POSITIVE-NAND GATE
(Texas Instruments)
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
description
These devic.
74F1056 - 8-Bit Schottky Barrier Diode Array
(Fairchild Semiconductor)
74F1056 8-Bit Schottky Barrier Diode Array
December 1993 Revised August 1999
74F1056 8-Bit Schottky Barrier Diode Array
General Description
The 74F1.
74F1071 - 18-Bit Undershoot/Overshoot Clamp
(Fairchild Semiconductor)
74F1071 18-Bit Undershoot/Overshoot Clamp
October 1994 Revised August 1999
74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device
Gener.
74F109 - Dual JK Positive Edge-Triggered Flip-Flop
(National Semiconductor)
54F/74F109
54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
November 1994
54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
General Descript.
74F109 - Positive J-K positive edge-triggered flip-flops
(NXP)
INTEGRATED CIRCUITS
74F109 Positive J-K positive edge-triggered flip-flops
Product specification IC15 Data Handbook 1990 Oct 23
Philips Semiconducto.
74F109 - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP
(Texas Instruments)
SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS047A – MARCH 1987 – REVISED OCTOBER 1993
• Package Options I.
74F11 - Triple 3-Input AND Gate
(National Semiconductor)
74F11 Triple 3-Input AND Gate
April 1988 Revised September 2000
74F11 Triple 3-Input AND Gate
General Description
This device contains three indepen.
Stock and price
TAGS
