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74F112 Datasheet - Fairchild Semiconductor

Dual JK Negative Edge-Triggered Flip-Flop

74F112 General Description

The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change.

74F112 Datasheet (59.08 KB)

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Datasheet Details

Part number:

74F112

Manufacturer:

Fairchild Semiconductor

File Size:

59.08 KB

Description:

Dual jk negative edge-triggered flip-flop.

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74F112 Dual Negative Edge-Triggered Flip-Flop Fairchild Semiconductor

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