74S112 - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

Datasheet Summary

Description

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.

The J and K data is processed by the flip-flops on the falling edge of the clock pulse.

Fairchild Semiconductor

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Datasheet Details

Part number	74S112
Manufacturer	Fairchild Semiconductor
File Size	42.41 KB
Description	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
Datasheet	74S112 Datasheet
Additional preview pages of the 74S112 datasheet.

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DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. Data on the J and K inputs can be changed while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated.

Published: Aug 29, 2014 |