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74S112 Datasheet - Fairchild Semiconductor

74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the neg.

74S112-FairchildSemiconductor.pdf

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Datasheet Details

Part number:

74S112

Manufacturer:

Fairchild Semiconductor

File Size:

42.41 KB

Description:

Dual negative-edge-triggered master-slave j-k flip-flop.

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74S112 74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop Fairchild Semiconductor

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