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74S139 - Decoder/Demultiplexer

This page provides the datasheet information for the 74S139, a member of the 74S138 Decoder/Demultiplexer family.

Datasheet Summary

Description

These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times.

In high-performance memory systems these decoders can be used to minimize the effects of system decoding.

Features

  • s Designed specifically for high speed: Memory decoders Data transmission systems s DM74S138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception s DM74S139 contains two fully independent 2-to-4-line decoders/demultiplexers s Schottky clamped for high performance s Typical propagation delay time (3 levels of logic) DM74S138 8 ns DM74S139 7.5 ns s Typical power dissipation DM74S138 245 mW DM74S139 300 mW Ordering Code: Order Number DM74S138N DM74S139N Pac.

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Datasheet preview – 74S139

Datasheet Details

Part number 74S139
Manufacturer Fairchild Semiconductor
File Size 73.34 KB
Description Decoder/Demultiplexer
Datasheet download datasheet 74S139 Datasheet
Additional preview pages of the 74S139 datasheet.

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Full PDF Text Transcription

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DM74S138 • DM74S139 Decoder/Demultiplexer August 1986 Revised April 2000 DM74S138 • DM74S139 Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The DM74S138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs.
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